The present invention relates to a semiconductor device and a method for manufacturing the same that prevents a Gate Induced Drain Leakage (GIDL) to improve a refresh characteristic of the semiconductor device.
In general, a semiconductor memory device comprises of a plurality of unit cells, each including one capacitor and one transistor. The capacitor is used to temporarily store data, and the transistor is used to transfer data between a bit line and the capacitor according to a control signal (word line) using the characteristics of a semiconductor changing an electric conductivity according to an environment. The transistor is composed of three regions including a gate, a source, and a drain. Charge transfer occurs between the source and the drain according to a control signal input to the gate. The charge transfer between the source and the drain is achieved through a channel region using the characteristics of the semiconductor.
To form a transistor on a semiconductor substrate, a gate is formed on the semiconductor substrate and impurities are doped on both sides of the gate to form a source and a drain. In order to increase the data storage capacity of the semiconductor memory device, the size of unit cells needs to be reduced. As the design rule of the capacitor and the transistor comprising the unit cell is decreased, the channel length of a cell transistor becomes gradually reduced. This results in a short channel effect and Drain Induced Barrier Lower (DIBL) occurs, thereby deteriorating the reliability of the transistor characteristics. A phenomena occurring due to the reduction in the channel length can be solved by maintaining a threshold voltage so that the cell transistor may perform a normal operation. In general, the shorter the transistor channel, the larger a doping density of impurities is needed in a channel formation region.
However, when the design rule is reduced to less than 100 nm, a is doping density of impurities in a channel formation region would need to be increased correspondingly. This increases an electric field in a storage node (SN) junction, thereby deteriorating a refresh characteristic of the semiconductor memory device. To prevent the refresh characteristic, a cell transistor having a three dimensional channel structure is used in which a channel is formed in a vertical direction so that a channel length of a transistor can be maintain in spite of a reduction of the design rule. Namely, although a channel dimension in a horizontal direction is short, the doping density can be reduced since the overall channel length is increased by providing a vertical dimension to the channel, thereby preventing the refresh characteristic from being deteriorated.
In addition, with the higher integration of a semiconductor device, there is a shorter distance between a word line and a bit line connected to a cell transistor. As a result, parasitic capacitance is increased to deteriorate an operation margin of a sense amplifier amplifying data transferred through the bit line. This has a bad influence upon the operation reliability of a semiconductor device. A buried word line structure has been proposed to reduce the parasitic capacitance between a bit line and a word line. In this case, in the buried word line structure, the word line is formed within a recess formed on a semiconductor substrate instead of on a surface the substrate. In the buried word line structure, a conductive material is formed in the recess formed in the semiconductor substrate, and an upper portion of the conductive material is covered with an insulating layer to bury the word line in the semiconductor substrate. Accordingly, electric isolation with the bit line formed on the semiconductor substrate on which source/drain are disposed can be clearly achieved.
However, in the buried word line structure, a Gate Induced Drain Leakage (GIDL) characteristic of the semiconductor device between an N-type junction of an active region and a conductive material (gate electrode) is magnified, thereby deteriorating a refresh characteristic of the semiconductor device.